1. Field of the Invention
This invention relates to a planarization method for semiconductor device, more particularly to a planarization method for semiconductor device capable of obtaining the global planarization with a selective CMP by simply performing surface treatment at an O3-TEOS layer.
2. Description of the Related Art
As the integrity of integrated circuits increases, a global planarization of interlayer dielectric by using CMP (Chemical Mechanical Polishing) is became necessary to meet the requirements of lithography process. The CMP is a planarization method by performing simultaneously a chemical reaction due to slurry and a mechanical process due to polishing pad. This method has an advantage of global planarization at a wide range of region that is impossible for the conventional BPSG(Boron-Phosphorous-Silicate-Glass) reflow or the SOG(Spin-On-Glass) etch-back, also the CMP is able to perform a low temperature planarization.
Meanwhile, at the manufacturing of integrated circuits, when the spacing between patterns is small, for example the spacing is below 0.3 xcexcm, gap filling matter is raised as a problem to be solved. And as solutions, HDP-CVD(High Density Plasma Chemical Vapor Deposition) manner, spin-on polymer coating manner and deposition of O3-TEOS(Ozon-Tetra Ethyl Ortho Silicate) layer having excellent surface mobility have been proposed.
However, since the O3-TEOS layer used to achieve the gap filling performance has a porous structure, an annealing step is further required to increase density of the O3-TEOS layer after the deposition step. Although the density is increased by the annealing step, its layer quality is still inferior to that of a thermal oxide. Therefore, according to those results of CMP on the O3-TEOS layer, a dishing is occurred at the regions of wide spacing between patterns. This dishing is also found not only in the O3-TEOS layer but also in oxide layers and metals such as tungsten.
In the aspect of planarity, global planarity is affected by feature height, size, layout, density and polishing condition such as polishing mechanical parameters, pad and slurry. When the active area is wide and feature height is high, it is difficult to get planarized surface without additional scheme as mentioned above.
The CMP provides not the global planarity but excellent local planarity. Therefore, a selective CMP has been proposed to obtain excellent global planarity without occurring dishing. The selective CMP is believed to be a very useful polishing method of achieving global planarization since selective CMP uses polishing selectivity of materials to be polished simultaneously.
FIGS. 1A to 1C are sectional views illustrating a planarization method for semiconductor device in prior art using the selective CMP.
Referring to FIG. 1A, metal patterns 2 are formed on a semiconductor substrate 1 by an etching process using a hard mask layer 3. Those metal patterns 2 are formed to get pattern densities that are various depending on regions. An O3-TEOS layer 4 having excellent gap filling characteristics is deposited over the semiconductor substrate 1. At this time, deposition thickness of the O3-TEOS layer 4 is thicker at a portion having the metal pattern 2 than at a portion not having the metal pattern 2. And the deposition thickness is also thicker at a portion having high pattern density than at a portion having low pattern density. A BN layer or SiN layer, more preferably a BN layer 5 is formed on the O3-TEOS layer 4 by a conventional plasma system having various depositing RF power.
Referring to FIG. 1B, the BN layer 5 is polished by the CMP step. Herein, the EN layer 5 over a region where the metal pattern 2 is formed, is polished while the BN layer 5 over wide range of regions where no metal pattern 2 is formed, is not polished and remained.
Referring to FIG. 1C, the O3-TEOS layer 4 and the remained BN layer 5 are continuously polished by the CMP step until the hard mask layer 3 is exposed. As a result, global planarization is accomplished. Herein, as known in the art, the BN layer 5 has high polishing selectivity with respect to oxide layers or metals. For instance, the polishing rate of the BN layer 5 is slower than that of the oxide layers and metals. Accordingly, during the CMP step, the O3-TEOS layer 4 is rapidly removed while the BN layer 5 is slowly removed. Therefore, the global planarization is obtained without occurring dishing at the wide range of region where no metal pattern 2 is formed.
However, the above described selective CMP requires additional BN depositing step thereby increasing manufacturing cost and decreasing production yield. Furthermore, device characteristics may be degraded by particles generated during the deposition step.
Therefore, the object of the present invention is to provide a planarization method for semiconductor device capable of obtaining the global planarization with a selective CMP without occurring any cost increase, degraded production yield or particle generation.
To accomplish the foregoing object of the present invention, the planarization method comprises following steps of: providing a semiconductor substrate in which metal patterns with various pattern densities are formed; depositing a porous oxide layer over the semiconductor substrate so as to cover the metal patterns; plasma-treating surface of the porous oxide layer; and polishing the plasma-treated porous oxide layer.
According to the present invention, an O3-TEOS layer or PECVD oxide layer is used as porous oxide layer.
Further, according to the present invention, N2O or NH3 gas is used as a plasma source gas during the plasma-treating step of the porous oxide layer, so that the surface of porous oxide layer is nitrified.
Also, according to the present invention, Ar, He or Ne gas is used as a plasma source gas during the plasma-treating step of the porous oxide layer, so that the surface of porous oxide layer is hardened.